Invited Speakers 2011
Rich Vuduc, Georgia Tech, USA
James R. Reinders, Intel, USA


Abstracts of Invited Talks

Balance principles for algorithm-architecture co-design

Richard Vuduc, Georgia Institute of Technology, USA

Slides in pdf-format are vailable here
Given an algorithm, what processor and memory architecture will deliver the best performance and power/energy efficiency? Conversely, given an architecture, what class of algorithms will (or will not) run efficiently? We are developing a novel analytical framework to answer these kinds of co-design questions, based on the concept of balance principles. A balance principle is a theoretical constraint equation that explicitly relates algorithm parameters to hardware parameters according to some figure of merit, such as speed, power, or cost. This notion originates in early work by Kung (1986) and others; however, we reinterpret the classical notions of balance in a modern context of parallel and I/O-efficient algorithm design as well as trends in emerging architectures. From such a principle, we argue that one can better understand algorithm and hardware trends, and furthermore gain insight into how to improve both algorithms and hardware. We use this principle to make quantitative predictions about future supercomputer systems as we proceed toward exascale machines. These predictions include when matrix multiply might becomememory-bound; for what algorithms stacking processors and memory will be beneficial, and for which it will not; and whether supercomputers based on embedded CPU-like processors or those based on GPU-like processors will be better and why. Our overall aim is to suggest how to one might co-design rigorously and quantitatively while still yielding intuition and insight.

Short Bio of Richard Vuduc:
Rich Vuduc is an assistant professor in the School of Computational Science and Engineering (CSE), within the College of Computing at Georgia Tech. He received his Ph.D. in Computer Science from the University of California, Berkeley, in January 2004, in the BeBOP group, under Profs. James Demmel and Katherine Yelick. He was a post-doctoral researcher in the Center for Applied Scientific Computing at the Lawrence Livermore National Laboratory, where he worked with Dr. Dan Quinlan on the ROSE project. His research area is high performance computing. Rich is developing automated tools and techniques to tune, to analyze, and to debug software for parallel machines, including emerging high-end multi/manycore architectures and accelerators. He focuses on applying these methods to CSE applications, which include computer-based simulation of natural and engineered systems and analysis of massive data sets.

 

Only the First Steps of the Parallel Evolution have been taken thus far

James R. Reinders, Intel USA

Slides in pdf-format

Parallel programming is wide spread but the changes in hardware and software have really only just started. James Reinders will discuss the evolution to parallelism so far, where we are headed in the future, and comment on projects he is involved in to help. James will explain why the term "heterogeneous" is a distraction on the road to the inevitable trend to specialization. James will explain how to be ready for an even more diverse future and highlight how to pick programming investments that are best aligned with the future.

Short Bio of James R. Reinders:
James Reinders is an expert in the area of parallelism, Intel’s leading spokesperson on tools for parallelism, and author of the O’Reilly Nutshell book on the C++ extensions for parallelism provided by the popular Intel Threading Building Blocks. James has decades of experience with high degrees of parallelism having worked on groundbreaking compilers and architectures such as the systolic arrays WARP and iWarp, and the world’s first TeraFLOP supercomputer (ASCI Red). James is author and co-author of several books in addition to the recent Threading Building Blocks Nutshell book.